Silicon carbide semiconductor device and method for manufacturing same

ABSTRACT

A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. patent application Ser. No.14/906,482, filed Jan. 20, 2016, which is a 371 application ofInternational Application No. PCT/JP2014/065312, filed Jun. 10, 2014,which claims the benefit of Japanese Patent Application No. 2013-155671,filed Jul. 26, 2013.

TECHNICAL FIELD

The present invention relates to a silicon carbide semiconductor deviceand a method for manufacturing the silicon carbide semiconductor device,in particular, a silicon carbide semiconductor device provided with atrench and a method for manufacturing the silicon carbide semiconductordevice.

BACKGROUND ART

In recent years, in order to achieve high breakdown voltage, low loss,and utilization of semiconductor devices, such as a MOSFET (Metal OxideSemiconductor Field Effect Transistor), under a high temperatureenvironment, silicon carbide has begun to be adopted as a material for asemiconductor device. Silicon carbide is a wide band gap semiconductorhaving a band gap larger than that of silicon, which has beenconventionally widely used as a material for semiconductor devices.Hence, by adopting silicon carbide as a material for a semiconductordevice, the semiconductor device can have a high breakdown voltage,reduced on resistance, and the like. Further, the semiconductor devicethus adopting silicon carbide as its material has characteristics lessdeteriorated even under a high temperature environment than those of asemiconductor device adopting silicon as its material, advantageously.

Japanese National Patent Publication No. 2000-509559 (Patent Document 1)describes a silicon carbide field effect transistor having a gatetrench. The silicon carbide field effect transistor includes: a p regionprovided near the bottom portion of a gate trench; and a source contactin contact with the p region.

CITATION LIST Patent Document

PTD 1: Japanese National Patent Publication No. 2000-509559

SUMMARY OF INVENTION Technical Problem

However, according to the silicon carbide field effect transistordescribed in Japanese National Patent Publication No. 2000-509559, it isdifficult to sufficiently relax electric field concentration at a cornerportion of the gate trench.

The present invention has been made to solve the problem describedabove, and has an object to provide a silicon carbide semiconductordevice in which electric field concentration at a corner portion of atrench can be effectively relaxed, as well as a method for manufacturingsuch a silicon carbide semiconductor device.

Solution to Problem

A silicon carbide semiconductor device according to the presentinvention includes a silicon carbide layer. The silicon carbide layerhas a first main surface and a second main surface opposite to the firstmain surface. The silicon carbide layer includes a drift region, a bodyregion, and a source region. The drift region constitutes the first mainsurface and has a first conductivity type. The body region is providedon the drift region and has a second conductivity type different fromthe first conductivity type. The source region is provided on the bodyregion to be separated from the drift region, constitutes the secondmain surface, and has the first conductivity type. The silicon carbidelayer is provided with a trench including a first side wall portion anda first bottom portion, the first side wall portion extending from thesecond main surface to the drift region through the source region andthe body region, the first bottom portion being in the drift region. Thesilicon carbide layer includes a second conductivity type region that isembedded in the drift region to face the first bottom portion and thathas the second conductivity type. The second conductivity type region iselectrically connected to the source region.

A method for manufacturing a silicon carbide semiconductor deviceaccording to the present invention includes the following steps. Thereis prepared a silicon carbide layer having a first main surface and asecond main surface opposite to the first main surface. A trench isformed in the second main surface of the silicon carbide layer. Thesilicon carbide layer includes a drift region, a body region, and asource region. The drift region constitutes the first main surface andhas a first conductivity type. The body region is provided on the driftregion and has a second conductivity type different from the firstconductivity type. The source region is provided on the body region tobe separated from the drift region, constitutes the second main surface,and has the first conductivity type. The trench includes a first sidewall portion and a first bottom portion, the first side wall portionextending from the second main surface to the drift region through thesource region and the body region, the first bottom portion being in thedrift region. The silicon carbide layer includes a second conductivitytype region that is embedded in the drift region to face the firstbottom portion and that has the second conductivity type. The secondconductivity type region is electrically connected to the source region.

Advantageous Effects of Invention

According to the present invention, there are provided a silicon carbidesemiconductor device in which electric field concentration at a cornerportion of a trench can be effectively relaxed, as well as a method formanufacturing such a silicon carbide semiconductor device.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic cross sectional view showing a configuration of asilicon carbide semiconductor device according to a first embodiment ofthe present invention.

FIG. 2 is a schematic plan view showing the configuration of the siliconcarbide semiconductor device according to the first embodiment of thepresent invention.

FIG. 3 is a schematic cross sectional view in a region of FIG. 2.

FIG. 4 is a flowchart schematically showing a method for manufacturing asilicon carbide semiconductor device according to the first embodimentof the present invention.

FIG. 5 is a schematic cross sectional view schematically showing a firststep of the method for manufacturing the silicon carbide semiconductordevice according to the first embodiment of the present invention.

FIG. 6 is a schematic cross sectional view schematically showing asecond step of the method for manufacturing the silicon carbidesemiconductor device according to the first embodiment of the presentinvention.

FIG. 7 is a schematic cross sectional view schematically showing a thirdstep of the method for manufacturing the silicon carbide semiconductordevice according to the first embodiment of the present invention.

FIG. 8 is a schematic cross sectional view showing a configuration of asilicon carbide semiconductor device according to a second embodiment ofthe present invention.

FIG. 9 is a schematic plan view showing the configuration of the siliconcarbide semiconductor device according to the second embodiment of thepresent invention.

FIG. 10 is a schematic cross sectional view showing a configuration of asilicon carbide semiconductor device according to a third embodiment ofthe present invention.

FIG. 11 is a schematic cross sectional view showing the configuration ofthe silicon carbide semiconductor device according to the thirdembodiment of the present invention.

FIG. 12 is a flowchart schematically showing a method for manufacturingthe silicon carbide semiconductor device according to the thirdembodiment of the present invention.

FIG. 13 is a schematic cross sectional view schematically showing afirst step of the method for manufacturing the silicon carbidesemiconductor device according to the third embodiment of the presentinvention.

FIG. 14 is a schematic cross sectional view schematically showing asecond step of the method for manufacturing the silicon carbidesemiconductor device according to the third embodiment of the presentinvention.

FIG. 15 is a schematic cross sectional view schematically showing athird step of the method for manufacturing the silicon carbidesemiconductor device according to the third embodiment of the presentinvention.

FIG. 16 is a schematic cross sectional view showing a configuration of asilicon carbide semiconductor device according to a fourth embodiment ofthe present invention.

FIG. 17 is a schematic cross sectional view showing a configuration of asilicon carbide semiconductor device according to a fifth embodiment ofthe present invention.

FIG. 18 is a schematic cross sectional view showing a configuration of asilicon carbide semiconductor device according to a sixth embodiment ofthe present invention.

FIG. 19 is a schematic cross sectional view showing a configuration of asilicon carbide semiconductor device according to a seventh embodimentof the present invention.

FIG. 20 is a flowchart schematically showing a method for manufacturingthe silicon carbide semiconductor device according to the seventhembodiment of the present invention.

DESCRIPTION OF EMBODIMENTS Description of Embodiments of the Inventionof the Present Application

The following describes embodiments of the present invention based onfigures. It should be noted that in the below-described figures, thesame or corresponding portions are given the same reference charactersand are not described repeatedly. Regarding crystallographic indicationsin the present specification, an individual orientation is representedby [ ], a group orientation is represented by < >, and an individualplane is represented by ( ) and a group plane is represented by { }. Inaddition, a negative crystallographic index is normally expressed byputting “-” (bar) above a numeral, but is expressed by putting thenegative sign before the numeral in the present specification.

(1) A silicon carbide semiconductor device 1 according to an embodimentincludes a silicon carbide layer 10. Silicon carbide layer 10 has afirst main surface 10 b and a second main surface 10 a opposite to firstmain surface 10 b. Silicon carbide layer 10 includes a drift region 81,a body region 82, and a source region 83. Drift region 81 constitutesfirst main surface 10 b and has a first conductivity type. Body region82 is provided on drift region 81 and has a second conductivity typedifferent from the first conductivity type. Source region 83 is providedon body region 82 to be separated from drift region 81, constitutessecond main surface 10 a, and has the first conductivity type. Siliconcarbide layer 10 is provided with a trench TR including a first sidewall portion SW1 and a first bottom portion BT1, first side wall portionSW1 extending from second main surface 10 a to drift region 81 throughsource region 83 and body region 82, first bottom portion BT1 being indrift region 81. Silicon carbide layer 10 includes a second conductivitytype region 2 that is embedded in drift region 81 to face first bottomportion BT1 and that has the second conductivity type. Secondconductivity type region 2 is electrically connected to source region83.

According to silicon carbide semiconductor device 1 according to theabove-described embodiment, silicon carbide layer 10 includes secondconductivity type region 2 that is embedded in drift region 81 to facebottom portion BT1 of trench TR and that has the second conductivitytype. This makes it possible to effectively relax electric fieldconcentration at corner portion 81 a at which first bottom portion BT1and first side wall portion SW1 of trench TR are in contact with eachother. As a result, the breakdown voltage of the silicon carbidesemiconductor device can be improved effectively. Moreover, secondconductivity type region 2 is electrically connected to source region83. Accordingly, depletion is facilitated when drain voltage is applied,thereby facilitating decrease of capacitance. Accordingly, the siliconcarbide semiconductor device is improved in high speed responsiveness,thereby improving a switching characteristic.

(2) Preferably in silicon carbide semiconductor device 1 according to(1), second conductivity type region 2 has a mesh structure when viewedin a plan view. Accordingly, while securing a wide current path,electric field concentration at corner portion 81 a of trench TR can berelaxed.

(3) Preferably, silicon carbide semiconductor device 1 according to (1)or (2) further includes a metal region 96. Metal region 96 is in contactwith source region 83. Source region 83 and second conductivity typeregion 2 are electrically connected to each other via metal region 96.Accordingly, the switching characteristic of the silicon carbidesemiconductor device can be improved effectively. Here, the expression“source region 83 and second conductivity type region 2 are electricallyconnected to each other via metal region 96” is intended to indicatethat metal region 96 is included in a portion of an electric circuitconnecting source region 83 and second conductivity type region 2 toeach other, and is intended to include a case where the electric circuitconnecting source region 83 and second conductivity type region 2 toeach other has an electrically conductive region other than metal region96.

(4) Preferably in silicon carbide semiconductor device 1 according to(3), silicon carbide layer 10 is provided with a stepped portion STincluding a second bottom portion BT2 and a second side wall portionSW2, second bottom portion BT2 being between first main surface 10 b andsecond main surface 10 a, second side wall portion SW2 connecting secondbottom portion BT2 and second main surface 10 a to each other. Metalregion 96 is in contact with source region 83 in second main surface 10a and is in contact with second bottom portion BT2. Accordingly, secondconductivity type region 2 can be electrically connected to sourceregion 83 effectively.

(5) Preferably in silicon carbide semiconductor device 1 according to(4), silicon carbide layer 10 includes a termination region OR and anelement region IR surrounded by termination region OR. Stepped portionST is provided in termination region OR. Accordingly, secondconductivity type region 2 can be electrically connected to sourceregion 83 while securing a wide element region IR.

(6) Preferably in silicon carbide semiconductor device 1 according to(5), termination region OR has a guard ring region 3 having the secondconductivity type. Metal region 96 is in contact with guard ring region3 at second bottom portion BT2, and guard ring region 3 is in contactwith second conductivity type region 2. Accordingly, the breakdownvoltage of the silicon carbide semiconductor device can be improved.

(7) Preferably in silicon carbide semiconductor device 1 according to(6), termination region OR includes a field stop region 4 that surroundsguard ring region 3 when viewed in a plan view and that has the firstconductivity type. Field stop region 4 is spaced from second mainsurface 10 a. Accordingly, the breakdown voltage of the silicon carbidesemiconductor device can be improved more.

(8) Preferably in silicon carbide semiconductor device 1 according to(5), metal region 96 is directly in contact with second conductivitytype region 2 at second bottom portion BT2. Accordingly, the switchingcharacteristic of the silicon carbide semiconductor device can beimproved more.

(9) Preferably in silicon carbide semiconductor device 1 according to(4), silicon carbide layer 10 includes a termination region OR and anelement region IR surrounded by termination region OR. Stepped portionST is provided in element region IR. Accordingly, the whole of secondconductivity type region 2 can be provided with the same potential asthe source region in a short time.

(10) Preferably in silicon carbide semiconductor device 1 according to(9), metal region 96 is directly in contact with second conductivitytype region 2 at second bottom portion BT2. Accordingly, the switchingcharacteristic of the silicon carbide semiconductor device can beimproved more.

(11) Preferably in silicon carbide semiconductor device 1 according to(1) or (2), source region 83 is in contact with second conductivity typeregion 2 via body region 82 and a JTE region 5 having the secondconductivity type. Accordingly, metal region 96 does not need to beformed in order to connect source region 83 and the second conductivitytype region to each other, thereby simplifying the manufacturing processof silicon carbide semiconductor device 1.

(12) Preferably in silicon carbide semiconductor device 1 according toany one of (1) to (11), first bottom portion BT1 of trench TR extends tosurround a polygonal cell CL when viewed in a plan view, and when viewedin a plan view, second conductivity type region 2 is provided at alocation at which an apex 81 a of cell CL overlaps with secondconductivity type region 2. Apex 81 a of cell CL is a location at whichthe electric field is likely to be particularly concentrated in thecorner portion of trench TR. By providing second conductivity typeregion 2 to overlap with apex 81 a of cell CL, the electric fieldconcentration in corner portion 81 a of trench TR can be relaxedeffectively.

(13) A method for manufacturing a silicon carbide semiconductor device 1according to an embodiment includes the following steps. There isprepared a silicon carbide layer 10 having a first main surface 10 b anda second main surface 10 a opposite to first main surface 10 b. A trenchTR is formed in second main surface 10 a of silicon carbide layer 10.Silicon carbide layer 10 includes a drift region 81, a body region 82,and a source region 83. Drift region 81 constitutes first main surface10 b and has a first conductivity type. Body region 82 is provided ondrift region 81 and has a second conductivity type different from thefirst conductivity type. Source region 83 is provided on body region 82to be separated from drift region 81, constitutes second main surface 10a, and has the first conductivity type. Trench TR includes a first sidewall portion SW1 and a first bottom portion BT1, first side wall portionSW1 extending from second main surface 10 a to drift region 81 throughsource region 83 and body region 82, first bottom portion BT1 being indrift region 81. Silicon carbide layer 10 includes a second conductivitytype region 2 that is embedded in drift region 81 to face first bottomportion BT1 and that has the second conductivity type. Secondconductivity type region 2 is electrically connected to source region83.

According to a method for manufacturing silicon carbide semiconductordevice 1 according to the embodiment, silicon carbide layer 10 includessecond conductivity type region 2 that is embedded in drift region 81 toface first bottom portion BT1 of trench TR and that has secondconductivity type. This makes it possible to effectively relax electricfield concentration at corner portion 81 a at which first bottom portionBT1 and first side wall portion SW1 of trench TR are in contact witheach other. As a result, the breakdown voltage of the silicon carbidesemiconductor device can be improved effectively. Moreover, secondconductivity type region 2 is electrically connected to source region83. Accordingly, depletion is facilitated when drain voltage is applied,thereby facilitating decrease of capacitance. Accordingly, the siliconcarbide semiconductor device is improved in high speed responsiveness,thereby improving a switching characteristic.

(14) Preferably in the method for manufacturing silicon carbidesemiconductor device 1 according to (13), a stepped portion ST is formedin second main surface 10 a of silicon carbide layer 10, stepped portionST including a second bottom portion BT2 and a second side wall portionSW2, second bottom portion BT2 being between first main surface 10 b andsecond main surface 10 a, second side wall portion SW2 connecting secondbottom portion BT2 and second main surface 10 a to each other. A metalregion 96 is formed in contact with source region 83 and second bottomportion BT2. Accordingly, second conductivity type region 2 can beelectrically connected to source region 83 effectively.

(15) Preferably in method for manufacturing silicon carbidesemiconductor device 1 according to (14), stepped portion ST is formedby thermal etching. Accordingly, stepped portion ST can be formedeffectively.

Details of Embodiments of the Invention of the Present Application

Next, the embodiments of the present invention will be described more indetail.

First Embodiment

With reference to FIG. 1, the following describes a structure of aMOSFET 1 serving as a silicon carbide semiconductor device of a firstembodiment. MOSFET 1 according to the first embodiment includes asilicon carbide layer 10, a silicon carbide single crystal substrate 80,gate insulating films 91, gate electrodes 92, interlayer insulatingfilms 93, metal regions 96, and a drain electrode 98.

Silicon carbide layer 10 is an epitaxial layer made of silicon carbide,and includes a first main surface 10 b and a second main surface 10 aopposite to the first main surface. Silicon carbide single crystalsubstrate 80 is made of, for example, hexagonal silicon carbide singlecrystal having polytype 4H. First main surface 10 b of silicon carbidelayer 10 is in contact with silicon carbide single crystal substrate 80.Silicon carbide layer 10 mainly includes a drift region 81, body regions82, source regions 83, contact regions 84, a p type region 2, andconnection regions 2 a. Silicon carbide layer 10 includes an elementregion IR and a termination region OR surrounding element region IR (seeFIG. 10). Termination region OR may include a guard ring region 3 (seeFIG. 10) and a field stop region 4 (see FIG. 10).

Drift region 81 is an n type (first conductivity type) region includingan impurity such as nitrogen, for example. Drift region 81 constitutesfirst main surface 10 b of silicon carbide layer 10. Drift region 81 hasa lower drift region 81 c and an upper drift region 81 d. Upper driftregion 81 d is provided on lower drift region 81 c. P type region 2 ispartially provided in contact with an interface between lower driftregion 81 c and upper drift region 81 d. Drift region 81 preferably hasan impurity concentration lower than the impurity concentration ofsilicon carbide single crystal substrate 80. Drift region 81 preferablyhas a donor concentration of not less than 1×10¹⁵ cm⁻³ and not more than5×10¹⁶ cm⁻³, for example, 8×10¹⁵ cm⁻³. The thickness of lower driftregion 81 c and the thickness of upper drift region 81 d are 9 μm and 3respectively, for example.

Body region 82 is a p type (second conductivity type) region includingan impurity such as aluminum or boron, for example. Body region 82 isprovided on upper drift region 81 d. Body region 82 preferably has anacceptor concentration of not less than 1×10¹⁷ cm⁻³ and not more than5×10¹⁸ cm⁻³. The acceptor concentration of body region 82 is higher thanthe donor concentration of drift region 81.

Source region 83 is an n type region including an impurity such asphosphorus, for example. Source region 83 is provided on body region 82to be separated from drift region 81 by body region 82. Source region 83has a donor concentration of, for example, about 2×10¹⁹ cm⁻³. The donorconcentration of source region 83 is higher than the acceptorconcentration of body region 82. Source region 83 and contact region 84constitute second main surface 10 a of silicon carbide layer 10.

Contact region 84 is a p type region including an impurity such asaluminum, for example. Contact region 84 is provided to be surrounded bysource region 83 and is connected to body region 82. The acceptorconcentration of contact region 84 is higher than the acceptorconcentration of body region 82. The acceptor concentration of contactregion 84 is about 1×10²⁰ cm⁻³, for example. A cell CL is formed bycontact region 84, source region 84, body region 82, and drift region81.

A (gate) trench TR is provided in second main surface 10 a of siliconcarbide layer 10. Trench TR includes a first side wall portion SW1 and afirst bottom portion BT1. First side wall portion SW1 extends fromsecond main surface 10 a of silicon carbide layer 10 to upper driftregion 81 d through source region 83 and body region 82. First bottomportion BT1 is continuously connected to first side wall portion SW1,and is in upper drift region 81 d. On body region 82, first side wallportion SW1 includes a channel surface of MOSFET 1.

First side wall portion SW1 is inclined relative to second main surface10 a of silicon carbide layer 10. When viewed in a cross section (fieldof view in a direction parallel to first main surface 10 b), trench TRis expanded in a tapered manner toward its opening. In the presentembodiment, first bottom portion BT1 is substantially parallel to secondmain surface 10 a, and has a flat shape. A portion at which first bottomportion BT1 and first side wall portion SW1 are connected to each otheris a corner portion 81 b of trench TR.

Silicon carbide layer 10 is provided with stepped portions ST eachincluding: a second bottom portion BT2 between first main surface 10 band second main surface 10 a of silicon carbide layer 10; and a secondside wall portion SW2 that connects second bottom portion BT2 and secondmain surface 10 a to each other. In the present embodiment, steppedportion ST is provided in element region IR. Preferably, second bottomportion BT2 of stepped portion ST is provided at a location closer tofirst main surface 10 b relative to first bottom portion BT1 of trenchTR. Preferably, when viewed in a cross section, the width of secondbottom portion BT2 of stepped portion ST is wider than the width offirst bottom portion BT1 of trench TR. Stepped portion ST is providednot to constitute a part of the plurality of cells CL provided inelement region IR. The number of stepped portions ST is less than thenumber of cells CL.

Each of p type region 2 (second conductivity type region) and connectionregion 2 a is a p type region including an impurity such as aluminum,for example. P type region 2 is provided to be embedded in drift region81. P type region 2 is provided to be spaced from first bottom portionBT1 of trench TR. Preferably, p type region 2 is located at the firstmain surface 10 b side relative to first bottom portion BT1 of trenchTR. Preferably, p type region 2 is separated from body region 82 by notless than 1 μm and not more than 5 μm. Each of p type region 2 andconnection region 2 a has a dose amount of, for example, not less than1×10¹² cm⁻² and not more than 1×10¹⁵ cm⁻², preferably, not less than1×10¹³ cm⁻² and not more than 5×10¹³ cm⁻². Connection region 2 a isprovided in contact with second bottom portion BT2 of stepped portionST. Connection region 2 a and p type region 2 may be a p type region 2obtained by, for example, forming simultaneously connection region 2 aand p type region 2 to be substantially in one piece. In this case,metal region 96 is connected directly to p type region 2.

FIG. 2 shows a plane of MOSFET 1 taken along a region II-II of FIG. 1.With reference to FIG. 2, p type region 2 has a mesh structure whenviewed in a plan view (field of view in the normal direction of firstmain surface 10 b). In FIG. 2, a region of a hexagon (polygon)surrounded by a broken line represents a planar shape of upper driftregion 81 d when viewed at a location of first bottom portion BT1 oftrench TR. A region between adjacent hexagonal cells CL is first bottomportion BT1 of trench TR. In other words, when viewed in a plan view,first bottom portion BT1 of trench TR extends to surround hexagonal(polygonal) cell CL. When viewed in a plan view, p type region 2 isprovided at a location at which each of all the apexes 81 a of hexagonal(polygonal) cell CL overlaps with p type region 2.

An apex 81 a of hexagonal cell CL, which is a portion at which firstside wall portion SW1 and first bottom portion BT1 of trench TR crosseach other, is a first corner portion 81 a of trench TR, whereas aportion between two adjacent apexes of the hexagon is a second cornerportion 81 b of trench TR. In first corner portion 81 a, electric fieldconcentration is more likely to take place than that in second cornerportion 81 b, thus resulting in high electric field strength.Preferably, when viewed in a plan view, p type region 2 is provided at alocation overlapping with first corner portion 81 a of trench TR and notoverlapping with second corner portion 81 b of trench TR. Accordingly,electric field concentration at first corner portion 81 a of trench TRcan be relaxed effectively while securing a current path.

When viewed in a plan view, first bottom portion BT1 of trench TR has ahoneycomb structure. When viewed in a plan view, p type region 2 islocated at locations overlapping with intersections IS of the honeycombstructure, and has a mesh structure having a shape that does not overlapwith a portion of a line segment connecting two adjacent intersectionsIS of the honeycomb structure to each other. When viewed in a plan view,connection region 2 a has a shape of hexagon (polygon), for example. Asshown in FIG. 2, connection region 2 a is in contact with p type region2 at each of the apexes of the hexagon.

FIG. 3 shows a plane of MOSFET 1 taken along a region of FIG. 2. Withreference to FIG. 3, p type region 2 is provided at a location facing aportion of first bottom portion BT1 of trench TR when viewed in a crosssection. In other words, when viewed in a plan view, p type region 2 andfirst bottom portion BT1 of trench TR are partially overlapped with eachother. P type region 2 is provided at a location facing source region 83and body region 82. Moreover, p type region 2 is provided at a locationon a tangential line of first side wall portion SW1 and first bottomportion BT1 of trench TR so as to face apex 81 a of hexagonal cell CL.

With reference to FIG. 1, gate insulating film 91 covers each of firstside wall portion SW1 and first bottom portion BT1 of trench TR. Gateinsulating film 91 is provided on body region 82 to connect sourceregion 83 and upper drift region 81 d to each other. Gate insulatingfilm 91 may be in contact with second side wall portion SW2 and secondbottom portion BT2, which constitute stepped portion ST. Gate electrode92 is in contact with gate insulating film 91 and is provided in trenchTR. Interlayer insulating film 93 is provided in contact with gateelectrode 92 and gate insulating film 91 to electrically insulate gateelectrode 92 and a source electrode 94 from each other. Interlayerinsulating film 93 may be provided on gate insulating film 91 providedin contact with second side wall portion SW2 and second bottom portionBT2, which constitute stepped portion ST. Interlayer insulating film 93is made of, for example, silicon dioxide.

Metal region 96 includes source electrode 94, a source interconnectionlayer 95, and a contact electrode 94 a. Source electrode 94 is incontact with each of source region 83 and contact region 84. Sourceinterconnection layer 95 is provided on and in contact with sourceelectrode 94. Source interconnection layer 95 is, for example, analuminum layer. Interlayer insulating film 93 insulates between gateelectrode 92 and source interconnection layer 95. Contact electrode 94 ais in contact with connection region 2 a at second bottom portion BT2 ofstepped portion ST. Contact electrode 94 a may be in contact with gateinsulating film 91. Source interconnection layer 95 extends from sourceelectrode 94 to come into stepped portion ST via above interlayerinsulating film 93, and is in contact with contact electrode 94 a. Metalregion 96 is in contact with source region 83 and contact region 84 insecond main surface 10 a of silicon carbide layer 10 and is also incontact with second bottom portion BT2 of stepped portion ST.

Source region 83 is electrically connected to p type region 2 via metalregion 96. Source region 83 is in ohmic contact with source electrode94. Source region 83 is electrically connected to p type region 2 viasource electrode 94, source interconnection layer 95, contact electrode94 a, and connection region 2 a.

Preferably, each of first side wall portion SW1 of trench TR and secondside wall portion SW2 of stepped portion ST includes a special plane.The special plane is a plane including a first plane having a planeorientation of {0-33-8}. More preferably, the special planemicroscopically includes the first plane and microscopically furtherincludes a second plane having a plane orientation of {0-11-1}. Furtherpreferably, the first plane and the second plane include a combinedplane having a plane orientation of {0-11-2}. Moreover, the specialplane is a plane macroscopically having an off angle of 62°±10° relativeto the {000-1} plane.

Next, the following describes an example of a method for manufacturingMOSFET 1 serving as the silicon carbide semiconductor device accordingto the present embodiment.

First, a first epitaxial layer forming step (FIG. 4: S10) is performed.As shown in FIG. 5, lower drift region 81 c, which is to serve as aportion of drift region 81 (FIG. 1), is formed on silicon carbide singlecrystal substrate 80. Specifically, lower drift region 81 c is formed byepitaxial growth on silicon carbide single crystal substrate 80. Thisepitaxial growth can be achieved by employing a CVD (Chemical VaporDeposition) method that utilizes a mixed gas of silane (SiH₄) andpropane (C₃H₈) as a material gas and utilizes hydrogen gas (H₂) as acarrier gas, for example. On this occasion, an impurity (donor) such asnitrogen (N) or phosphorus (P) is preferably introduced as an impurity,for example. The concentration of the impurity in lower drift region 81c such as nitrogen is, for example, about 7.0×10¹⁵ cm³. The thickness oflower drift region 81 c is about 9 μm, for example.

Next, an embedded p type region forming step (FIG. 4: S20) is performed.In a portion of lower drift region 81 c, p type region 2 having p typeconductivity is formed. Specifically, acceptor ions (impurity ions forproviding second conductivity type) such as aluminum are implanted intolower drift region 81 c using an implantation mask (not shown), therebyforming p type region 2. The dose amount of aluminum ions is about3×10¹³ cm⁻², for example.

Next, a second epitaxial layer forming step (FIG. 4: S30) is performed.As shown in FIG. 6, after the formation of p type region 2, upper driftregion 81 d having n type is formed on lower drift region 81 c having ntype. Accordingly, p type region 2 is embedded in drift region 81constituted of lower drift region 81 c and upper drift region 81 d.Upper drift region 81 d can be formed by the same method as the methodfor forming lower drift region 81 c. The concentration of the impurityin upper drift region 81 d such as nitrogen is, for example, about1.0×10¹⁶ cm³. Upper drift region 81 d has a thickness of, for example,about 3 μm.

Next, body region 82 and source region 83 are formed on drift region 81.They can be formed by ion implantations into drift region 81, forexample. In the ion implantation for forming body region 82, ions of animpurity for providing p type such as aluminum (Al) are implanted.Meanwhile, in the ion implantation for forming source region 83, ions ofan impurity for providing n type conductivity such as phosphorus (P) areimplanted, for example. It should be noted that instead of the ionimplantations, epitaxial growth involving addition of impurities may beemployed.

Drift region 81, body region 82, source region 83, contact region 84,and p type region 2 constitute silicon carbide layer 10 having firstmain surface 10 b and second main surface 10 a. Drift region 81constitutes first main surface 10 b and source region 83 constitutessecond main surface 10 a. In this way, silicon carbide layer 10 isprepared which has first main surface 10 b and second main surface 10 aopposite to first main surface 10 b.

Next, a stepped portion forming step (FIG. 5: S40) is performed.Specifically, a mask layer (not shown) having an opening is formed onsecond main surface 10 a constituted of source region 83. As a masklayer, a silicon oxide film or the like can be used, for example. Theopening is formed in conformity with the location of stepped portion ST(FIG. 1).

In the opening of the mask layer, source region 83, body region 82, anda portion of drift region 81 are removed by etching. An exemplary,usable etching method is Reactive Ion Etching (RIE), in particular,Inductive Coupling Plasma (ICP) RIE. Specifically, for example, ICP-RIEcan be used which employs SF₆ or a mixed gas of SF₆ and O₂ as a reactivegas. With such etching, a recess having a side wall substantiallyperpendicular to second main surface 10 a is formed in the region inwhich stepped portion ST (FIG. 1) is to be formed.

Next, thermal etching is performed in the recess. This thermal etchingcan be performed by, for example, heating in an atmosphere containingreactive gas having at least one or more types of halogen atom. The atleast one or more types of halogen atom include at least one of chlorine(Cl) atom and fluorine (F) atom. This atmosphere is, for example, Cl₂,BCL₃, SF₆, or CF₄. For example, the thermal etching is performed using amixed gas of chlorine gas and oxygen gas as a reactive gas, at a heattreatment temperature of, for example, not less than 700° C. and notmore than 1000° C.

It should be noted that the reactive gas may contain a carrier gas inaddition to the chlorine gas and the oxygen gas. An exemplary, usablecarrier gas is nitrogen (N₂) gas, argon gas, helium gas, or the like.When the heat treatment temperature is set at not less than 700° C. andnot more than 1000° C. as described above, a rate of etching SiC isapproximately, for example, 70 μm/hour. In addition, in this case, themask layer, which is formed of silicon oxide and therefore has a verylarge selection ratio relative to SiC, is not substantially etchedduring the etching of SiC.

As shown in FIG. 7, by the thermal etching, stepped portion ST is formedin second main surface 10 a of silicon carbide layer 10. Stepped portionST includes: second side wall portion SW2 extending to drift region 81through source region 83 and body region 82; and second bottom portionBT2 located on drift region 81. Preferably, during the formation ofstepped portion ST, the special plane described above is spontaneouslyformed on second side wall portion SW2, in particular, on body region82. Next, the mask layer is removed by an appropriate method such asetching.

Next, an ion implantation step (FIG. 4: S50) is performed. An ionimplantation mask layer is formed on second main surface 10 a of siliconcarbide layer 10 to have an opening in conformity with regions in whichcontact region 84 (FIG. 1) and connection region 2 a (FIG. 1) are to beformed. Aluminum ions or the like are implanted into silicon carbidelayer 10 using the mask layer, thereby forming contact region 84 andconnection region 2 a both having p type conductivity. It should benoted that contact region 84 and connection region 2 a may be formedsimultaneously or may be formed separately.

Next, an activation annealing step (FIG. 4: S60) is performed. In orderto activate the impurity implanted in silicon carbide layer 10 by theion implantation step, heat treatment is performed onto silicon carbidelayer 10. This heat treatment is preferably performed at a temperatureof not less than 1500° C. and not more than 1900° C., for example, atemperature of approximately 1700° C. The heat treatment is performedfor approximately 30 minutes, for example. The atmosphere of the heattreatment is preferably an inert gas atmosphere, such as Ar atmosphere.

Next, a trench forming step (FIG. 5: S70) is performed. The trenchforming step can be performed in the same manner as that in the steppedportion forming step (FIG. 5: S40) described above. Specifically, a masklayer having an opening is formed on the surface constituted of sourceregion 83 and contact region 84. As the mask layer, a silicon oxide filmor the like can be used, for example. The opening is formed inconformity with the location of trench TR (FIG. 1). In the opening ofthe mask layer, source region 83, body region 82, and a portion of driftregion 81 are removed by etching. The etching is performed using ICP-RIEthat employs SF₆ or a mixed gas of SF₆ and O₂ as a reactive gas, forexample. With the etching, a recess having a side wall substantiallyperpendicular to second main surface 10 a is formed in the region inwhich trench TR (FIG. 1) is to be formed.

Next, thermal etching is performed in the recess. This thermal etchingcan be performed by, for example, heating in an atmosphere containingreactive gas having at least one or more types of halogen atom. The atleast one or more types of halogen atom include at least one of chlorine(CO atom and fluorine (F) atom. This atmosphere is, for example, Cl₂,BCL₃, SF₆, or CF₄. For example, the thermal etching is performed using amixed gas of chlorine gas and oxygen gas as a reactive gas, at a heattreatment temperature of, for example, not less than 700° C. and notmore than 1000° C. It should be noted that the reactive gas may containa carrier gas in addition to the chlorine gas and the oxygen gas. Anexemplary, usable carrier gas is nitrogen (N₂) gas, argon gas, heliumgas, or the like.

With the thermal etching, trench TR is formed in second main surface 10a of silicon carbide layer 10. Trench TR includes: a first side wallportion SW1 extending to drift region 81 through source region 83 andbody region 82; and first bottom portion BT1 in drift region 81. Each offirst side wall portion SW1 and first bottom portion BT1 is distant awayfrom p type region 2. Preferably, during the formation of trench TR, thespecial plane is spontaneously formed on first side wall portion SW1, inparticular, on body region 82. Next, the mask layer is removed by anappropriate method such as etching.

It should be noted that both the trench forming step (FIG. 4: S70) andthe stepped portion forming step (FIG. 4: S40) are performed employingthermal etching, but the thermal etching time in the stepped portionforming step may be longer than the thermal etching time in the trenchforming step. Accordingly, second bottom portion BT2 constitutingstepped portion ST is formed at a location closer to first main surface10 b relative to first bottom portion BT1 of trench TR. The depth oftrench TR, in other words, distance between second main surface 10 a ofsilicon carbide layer 10 and first bottom portion BT1 of trench TR inthe normal direction of first main surface 10 b of silicon carbide layer10 is, for example, about not less than 1.0 μm and not more than 1.8 μm.The depth of stepped portion ST, in other words, distance between secondmain surface 10 a of silicon carbide layer 10 and second bottom portionBT2 of stepped portion ST in the normal direction of first main surface10 b of silicon carbide layer 10 is, for example, about not less than1.1 μm and not more than 3.0 μm.

Next, a gate oxide film forming step (FIG. 4: S80) is performed. Gateinsulating film 91 is formed to cover first side wall portion SW1 andfirst bottom portion BT1 of trench TR and second side wall portion SW2and second bottom portion BT2 of stepped portion ST. Gate insulatingfilm 91 may be formed, for example, by thermal oxidation. After theformation of gate insulating film 91, NO annealing may be performedusing nitrogen monoxide (NO) gas as an atmospheric gas. A temperatureprofile has such a condition that the temperature is not less than 1100°C. and not more than 1300° C. and holding time is approximately 1 hour,for example. Accordingly, nitrogen atoms are introduced into aninterface region between gate insulating film 91 and body region 82. Asa result, formation of interface states in the interface region issuppressed, thereby achieving improved channel mobility. It should benoted that a gas other than the NO gas can be employed as theatmospheric gas as long as the nitrogen atoms can be thus introduced.After this NO annealing, Ar annealing may be further performed usingargon (Ar) as an atmospheric gas. The Ar annealing is preferablyperformed at a heating temperature equal to or higher than the heatingtemperature in the above-described NO annealing and lower than themelting point of gate insulating film 91. This heating temperature isheld for approximately 1 hour, for example. Accordingly, interfacestates are further suppressed from being formed in the interface regionbetween gate insulating film 91 and body region 82. It should be notedthat instead of the Ar gas, a different inert gas such as nitrogen gascan be employed as the atmospheric gas.

Next, a gate electrode forming step (FIG. 4: S90) is performed. Gateelectrode 92 is formed on and in contact with gate insulating film 91.Specifically, gate electrode 92 is formed on gate insulating film 91 tofill the region in trench TR with gate electrode 92. A method forforming gate electrode 92 can be performed by, for example, forming afilm of conductor or doped polysilicon and performing CMP (ChemicalMechanical Polishing).

Next, an interlayer insulating film forming step (FIG. 4: S100) isperformed. Interlayer insulating film 93 is formed on gate electrode 92and gate insulating film 91 so as to cover the exposed surface of gateelectrode 92. Interlayer insulating film 93 is formed on and in contactwith gate insulating film 93 formed on second side wall portion SW2 andsecond bottom portion BT2 both constituting stepped portion ST.

Next, a source electrode and drain electrode forming step (FIG. 4: S110)is performed. In order to form an opening in interlayer insulating film93 and gate insulating film 91, interlayer insulating film 93 and gateinsulating film 91 are etched. Through the opening, each of sourceregion 83 and contact region 84 is exposed on second main surface 10 a.Next, on second main surface 10 a, source electrode 94 is formed incontact with each of source region 83 and contact region 84.

Likewise, gate insulating film 91 and interlayer insulating film 93 areetched to expose connection region 2 a in second bottom portion BT2 ofstepped portion ST. Next, in second bottom portion BT2 of steppedportion ST, contact electrode 94 a is formed in contact with connectionregion 2 a. Contact electrode 94 a and source electrode 94 may be formedsimultaneously or may be formed separately. Next, source interconnectionlayer 95 is formed in contact with source electrode 94, contactelectrode 94 a, and interlayer insulating film 93. In this way, metalregion 96 is formed in contact with source region 83 and second bottomportion BT2 of stepped portion ST. Moreover, drain electrode 98 isformed on first main surface 10 b constituted of drift region 81, withsilicon carbide single crystal substrate 80 being interposedtherebetween.

Next, the following describes function and effect of MOSFET 1 serving asthe silicon carbide semiconductor device according to the firstembodiment.

According to MOSFET 1 according to the first embodiment, silicon carbidelayer 10 has p type region 2 that is embedded in drift region 81 to facefirst bottom portion BT1 of trench TR and that has p type. This makes itpossible to effectively relax electric field concentration at cornerportion 81 a at which first bottom portion BT1 and first side wallportion SW1 of trench TR are in contact with each other. As a result,the breakdown voltage of MOSFET 1 can be improved effectively. Moreover,p type region 2 is electrically connected to source region 83.Accordingly, depletion is facilitated when drain voltage is applied,thereby facilitating decrease of capacitance. Accordingly, MOSFET 1 isimproved in high speed responsiveness, thereby improving a switchingcharacteristic.

Moreover, according to MOSFET 1 according to the first embodiment, ptype region 2 has a mesh structure when viewed in a plan view.Accordingly, while securing a wide current path, electric fieldconcentration at corner portion 81 a of trench TR can be relaxed.Moreover, p type region 2 is expanded in one piece in drift region 81 tohave the mesh structure. If there are a plurality of p type regions 2and are isolated from one another, source electrode 94 needs to beelectrically connected to each p type region 2. In this case, in orderto electrically connect source electrode 94 to each of the plurality ofp type regions 2, a multiplicity of source trenches need to be formed.On the other hand, according to MOSFET 1 according to the firstembodiment, p type region 2 is in one piece to have the mesh structure.Hence, a multiplicity of source trenches do not need to be provided toelectrically connect p type regions 2 and source electrodes 94 to oneanother, whereby cell pitch in MOSFET 1 can be reduced. As a result, theon resistance of MOSFET 1 can be reduced.

Further, MOSFET 1 according to the first embodiment further includesmetal region 96. Metal region 96 is in contact with source region 83.Source region 83 and p type region 2 are electrically connected to eachother via metal region 96. Accordingly, the switching characteristic ofMOSFET 1 can be improved effectively.

Furthermore, according to MOSFET 1 according to the first embodiment,silicon carbide layer 10 is provided with stepped portion ST constitutedof second bottom portion BT2 and second side wall portion SW2, secondbottom portion BT2 being between first main surface 10 b and second mainsurface 10 a, second side wall portion SW2 connecting second bottomportion BT2 and second main surface 10 a to each other. Metal region 96is in contact with source region 83 in second main surface 10 a, and isin contact with second bottom portion BT2. Accordingly, p type region 2can be electrically effectively connected to source region 83.

Furthermore, according to MOSFET 1 according to the first embodiment,silicon carbide layer 10 includes termination region OR and elementregion IR surrounded by termination region OR. Stepped portion ST isprovided in element region IR. Accordingly, the whole of p type region 2can be provided with the same potential as source region 83 in a shorttime.

Furthermore, according to MOSFET 1 according to the first embodiment,metal region 96 is directly in contact with p type region 2 in secondbottom portion BT2. Accordingly, the switching characteristic of MOSFET1 can be improved more.

Furthermore, according to MOSFET 1 according to the first embodiment,the first bottom portion of trench TR extends to surround polygonal cellCL when viewed in a plan view, and p type region 2 is provided at alocation at which apex 81 a of cell CL overlaps with p type region 2when viewed in a plan view. Apex 81 a of cell CL is a location at whichthe electric field is likely to be particularly concentrated in thecorner portion of trench TR. By providing p type region 2 to overlapwith apex 81 a of the cell, the electric field concentration in cornerportion 81 a of trench TR can be relaxed effectively.

According to a method for manufacturing MOSFET 1 according to the firstembodiment, silicon carbide layer 10 includes p type region 2 that isembedded in drift region 81 to face first bottom portion BT1 of trenchTR and that has p type. This makes it possible to effectively relaxelectric field concentration at corner portion 81 a at which firstbottom portion BT1 and first side wall portion SW1 of trench TR are incontact with each other. As a result, the breakdown voltage of MOSFET 1can be improved effectively. Moreover, p type region 2 is electricallyconnected to source region 83. Accordingly, depletion is facilitatedwhen drain voltage is applied, thereby facilitating decrease ofcapacitance. Accordingly, MOSFET 1 is improved in high speedresponsiveness, thereby improving a switching characteristic.

Further, according to the method for manufacturing MOSFET 1 according tothe first embodiment, stepped portion ST constituted of second bottomportion BT2 and second side wall portion SW2 is formed in second mainsurface 10 a of silicon carbide layer 10, second bottom portion BT2being between first main surface 10 b and second main surface 10 a,second side wall portion SW2 connecting second bottom portion BT2 andsecond main surface 10 a to each other. Metal region 96 is formed incontact with source region 83 and second bottom portion BT2.Accordingly, p type region 2 can be electrically effectively connectedto source region 83.

Furthermore, according to the method for manufacturing MOSFET 1according to the first embodiment, stepped portion ST is formed bythermal etching. Accordingly, stepped portion ST can be formedeffectively.

Second Embodiment

Next, the following describes a configuration of a MOSFET 1 according toa second embodiment. The configuration of MOSFET 1 according to thesecond embodiment is mainly different from the configuration of MOSFET 1according to the first embodiment in terms of the shape of p type region2. Apart from this, MOSFET 1 has substantially the same configuration asMOSFET 1 according to the first embodiment. The following mainlydescribes the difference from the configuration of MOSFET 1 according tothe first embodiment.

With reference to FIG. 8, p type region 2 of MOSFET 1 according to thesecond embodiment is provided at a location facing first bottom portionBT1 of trench TR. When viewed in a cross section, the width of p typeregion 2 in the direction parallel to first main surface 10 b may beless than the width of first bottom portion BT1 of trench TR. Connectionregion 2 a is provided in contact with contact electrode 94 a.Connection region 2 a may be in contact with gate insulating film 91 insecond bottom portion BT2 of stepped portion ST. When viewed in a crosssection, the width of connection region 2 a in the direction parallel tofirst main surface 10 b may be larger than the width of contactelectrode 94 a.

FIG. 9 shows a plane of MOSFET 1 taken along a region IX-IX of FIG. 8.With reference to FIG. 9, p type region 2 has a mesh structure whenviewed in a plan view. In FIG. 9, a region of a hexagon (polygon)surrounded by a broken line represents a planar shape of upper driftregion 81 d when viewed at a location of first bottom portion BT1 oftrench TR. A region between adjacent hexagonal cells CL is first bottomportion BT1 of trench TR. In other words, when viewed in a plan view,first bottom portion BT1 of trench TR extends to surround hexagonal cellCL. When viewed in a plan view, p type region 2 of MOSFET 1 according tothe second embodiment is provided to surround hexagonal cell CL.

When viewed in a plan view, first bottom portion BT1 of trench TR has ahoneycomb structure. P type region 2 is provided to overlap with firstbottom portion BT1 of trench TR when viewed in a plan view. That is, ptype region 2 also has a honeycomb structure. When viewed in a planview, connection region 2 a has a shape of hexagon (polygon), forexample. As shown in FIG. 9, connection region 2 a is in contact with ptype region 2 at each of the apexes of the hexagon.

Third Embodiment

Next, the following describes a configuration of a MOSFET 1 according toa third embodiment. MOSFET 1 according to the third embodiment isdifferent from the configuration of MOSFET 1 according to the firstembodiment in that stepped portion ST is provided in termination regionOR. Apart from this, MOSFET 1 according to the third embodiment hassubstantially the same configuration as that of MOSFET 1 according tothe first embodiment. The following mainly describes the difference fromthe configuration of MOSFET 1 according to the first embodiment.

With reference to FIG. 10, the following describes a structure of MOSFET1 serving as a silicon carbide semiconductor device of the thirdembodiment. Silicon carbide layer 10 of MOSFET 1 according to the thirdembodiment includes termination region OR and element region IRsurrounded by termination region OR. When viewed in a plan view,termination region OR includes: a plurality of guard ring regions 3provided to surround element region IR; and a field stop region 4provided to surround guard ring regions 3. Guard ring regions 3 have thesame conductivity type (second conductivity type) as p type region 2.The dose amount of guard ring region 3 may be less than the dose amountof p type region 2. The dose amount of acceptor ions such as aluminumions in guard ring region 3 is, for example, about 1.3×10¹³ cm⁻², andthe dose amount of acceptor ions such as aluminum ions in p type region2 is, for example, about 3.0×10¹³ cm⁻². Field stop region 4 is an n typeregion in which ions of phosphorus (P) or the like have been implanted,for example. The dose amount of donor ions such as phosphorous ions infield stop region 4 is, for example, about 1.0×10¹³ cm⁻².

Stepped portion ST is provided in second main surface 10 a of siliconcarbide layer 10. Second bottom portion BT2 of stepped portion ST isprovided in termination region OR of silicon carbide layer 10.Insulating film 91 is provided on second bottom portion BT2 of steppedportion ST, and insulating film 93 is provided on insulating film 91.Guard ring regions 3 and field stop region 4 are in contact withinsulating film 91 at second bottom portion BT2 of stepped portion ST. Aprotective film 97 is provided in contact with insulating film 93 andsource interconnection layer 95.

Termination region OR is a region including side end portion 10 d ofsilicon carbide layer 10 and external to the outermost cell. Sourceinterconnection layer 95 is provided to electrically connect sourceelectrode 94 and contact electrode 94 a to each other, source electrode94 being in contact with source region 83 and contact region 84 of thecell provided in element region IR, contact electrode 94 a being incontact with second bottom portion BT2 of stepped portion ST provided intermination region OR. Connection region 2 a is in contact with contactelectrode 94 a in second bottom portion BT2 of stepped portion ST.Connection region 2 a may be provided to extend from termination regionOR to element region IR.

FIG. 11 shows a plane of the MOSFET along a region XI-XI of FIG. 10.With reference to FIG. 11, p type region 2 has a mesh structure whenviewed in a plan view. In FIG. 11, a region of a hexagon (polygon)surrounded by a broken line represents a planar shape of upper driftregion 81 d when viewed at a location of first bottom portion BT1 oftrench TR. A region between adjacent hexagonal cells CL is first bottomportion BT1 of trench TR. In other words, when viewed in a plan view,first bottom portion BT1 of trench TR extends to surround hexagonal cellCL. When viewed in a plan view, p type region 2 is provided at alocation at which each of all the apexes 81 a of hexagonal cell CLoverlaps with p type region 2.

When viewed in a plan view, first bottom portion BT1 of trench TR has ahoneycomb structure. When viewed in a plan view, p type region 2 is atlocations overlapping with intersections IS of the honeycomb structure,and has a mesh structure having a shape that does not overlap with aportion of a line connecting intersections IS of the honeycomb structureto each other. When viewed in a plan view, connection region 2 a has ashape of hexagon (polygon), for example. As shown in FIG. 11, connectionregion 2 a is in contact with p type region 2 in the outer end portionof p type region 2 when viewed in a plan view.

When viewed in a plan view, guard ring regions 3 and field stop region 4are provided between p type region 2 and side end portion 10 d ofsilicon carbide layer 10. Guard ring regions 3 extend in the directionparallel to first main surface 10 b to surround p type region 2 andconnection region 2 a. Field stop region 4 is provided at the side endportion 10 d side of silicon carbide layer 10 relative to guard ringregions 3. P type region 2 may have a portion in termination region OR.

Next, the following describes an example of a method for manufacturingMOSFET 1 serving as the silicon carbide semiconductor device accordingto the third embodiment.

First, a first epitaxial layer forming step (FIG. 12: S10) is performed.The first epitaxial layer forming step is performed in the same manneras described in the first embodiment. Accordingly, lower drift region 81c is formed on silicon carbide single crystal substrate 80. Theconcentration of the impurity in lower drift region 81 c such asnitrogen is, for example, about 7.0×10¹⁵ cm³. The thickness of lowerdrift region 81 c is about 9 for example.

Next, an embedded p type region forming step (FIG. 12: S20) isperformed. As shown in FIG. 13, p type region 2, connection region 2 ahaving p type, guard ring regions 3 having p type, and field stop region4 having n type are formed in part of lower drift region 81 c.Specifically, an implantation mask (not shown) is used to implantacceptor ions such as aluminum into lower drift region 81 c, therebyforming p type region 2, connection region 2 a, and guard ring regions3. The dose amount of the acceptor ions such as aluminum ions in guardring regions 3 is, for example, about 1.3 to 1.5×10¹³ cm⁻², and the doseamount of the acceptor ions such as aluminum ions in p type region 2 is,for example, about 3.0×10¹³ cm⁻².

Next, a second epitaxial layer forming step (FIG. 12: S30) is performed.As shown in FIG. 14, after forming p type region 2, connection region 2a, guard ring regions 3, and field stop region 4, upper drift region 81d having n type is formed on lower drift region 81 c having n type.Accordingly, p type region 2, connection region 2 a, guard ring regions3, and field stop region 4 are embedded in drift region 81 constitutedof lower drift region 81 c and upper drift region 81 d. Upper driftregion 81 d can be formed by the same method as the method for forminglower drift region 81 c. The concentration of the impurity in upperdrift region 81 d such as nitrogen is, for example, about 1.0×10¹⁶ cm³.Upper drift region 81 d has a thickness of, for example, about 3 μm.

Next, an ion implantation step (FIG. 12: S50) is performed.Specifically, body region 82 and source region 83 are formed on driftregion 81. They can be formed by ion implantation into drift region 81,for example. In the ion implantation for forming body region 82, ions ofan impurity for providing p type such as aluminum (Al) are implanted.Meanwhile, in the ion implantation for forming source region 83, ions ofan impurity for providing n type conductivity such as phosphorus (P) areimplanted, for example. It should be noted that instead of the ionimplantation, epitaxial growth involving addition of impurities may beemployed.

Next, an ion implantation mask layer is formed on second main surface 10a of silicon carbide layer 10 to have an opening in conformity with theregion in which contact region 84 (FIG. 10) is to be formed. Aluminumions or the like are implanted into silicon carbide layer 10 using themask layer, thereby forming contact region 84 having p typeconductivity.

Next, an activation annealing step (FIG. 12: S60) is performed. In orderto activate the impurity implanted in silicon carbide layer 10 by theion implantation step, heat treatment is performed onto silicon carbidelayer 10. This heat treatment is preferably performed at a temperatureof not less than 1500° C. and not more than 1900° C., for example, atemperature of approximately 1700° C. The heat treatment is performedfor approximately 30 minutes, for example. The atmosphere of the heattreatment is preferably an inert gas atmosphere, such as Ar atmosphere.

Next, a trench forming step (FIG. 12: S70) is performed. In the trenchforming step, thermal etching described in the first embodiment isperformed. Accordingly, trench TR is formed in second main surface 10 aof silicon carbide layer 10. Trench TR includes: first side wall portionSW1 extending to drift region 81 through source region 83 and bodyregion 82; and first bottom portion BT1 on drift region 81. Each offirst side wall portion SW1 and first bottom portion BT1 is distant awayfrom p type region 2. Preferably, during the formation of trench TR, thespecial plane is spontaneously formed on first side wall portion SW1, inparticular, on body region 82.

Next, a stepped portion forming step (FIG. 12: S75) is performed. In thestepped portion forming step, the thermal etching described in the firstembodiment is performed. With the thermal etching, stepped portion ST isformed in second main surface 10 a of silicon carbide layer 10. Steppedportion ST includes: second side wall portion SW2 extending to driftregion 81 through source region 83 and body region 82; and second bottomportion BT2 on drift region 81. Preferably, during the formation ofstepped portion ST, the special plane described above is spontaneouslyformed on second side wall portion SW2, in particular, on body region82. Moreover, stepped portion ST is formed to expose a portion ofconnection region 2 a, guard ring regions 3, and field stop region 4 atsecond bottom portion BT2 of stepped portion ST. Stepped portion ST maybe formed to expose a portion of p type region 2 at second bottomportion BT2 of stepped portion ST. In this way, silicon carbide layer 10provided with trench TR and stepped portion ST shown in FIG. 15 isformed.

Next, a gate oxide film forming step (FIG. 12: S80) is performed. Gateinsulating film 91 is formed to cover first side wall portion SW1 andfirst bottom portion BT1 of trench TR and second side wall portion SW2and second bottom portion BT2 of stepped portion ST. Gate insulatingfilm 91 may be formed, for example, by thermal oxidation. After theformation of gate insulating film 91, NO annealing may be performedusing nitrogen monoxide (NO) gas as an atmospheric gas.

Next, a gate electrode forming step (FIG. 12: S90) is performed. Gateelectrode 92 is formed on and in contact with gate insulating film 91.Specifically, gate electrode 92 is formed on gate insulating film 91 tofill the region in trench TR with gate electrode 92. Gate electrode 92can be formed by, for example, forming a film of conductor or dopedpolysilicon and performing CMP.

Next, an interlayer insulating film forming step (FIG. 12: S100) isperformed. Interlayer insulating film 93 is formed on gate electrode 92and gate insulating film 91 to cover the exposed surface of gateelectrode 92. Interlayer insulating film 93 is formed on and in contactwith gate insulating film 93 formed on second side wall portion SW2 andsecond bottom portion BT2 both constituting stepped portion ST.

Next, a source electrode and drain electrode forming step (FIG. 12:S110) is performed. In order to form an opening in interlayer insulatingfilm 93 and gate insulating film 91, interlayer insulating film 93 andgate insulating film 91 are etched. Through the opening, each of sourceregion 83 and contact region 84 is exposed on second main surface 10 a.Next, on second main surface 10 a, source electrode 94 is formed incontact with each of source region 83 and contact region 84.

Likewise, gate insulating film 91 and interlayer insulating film 93 areetched to expose connection region 2 a in second bottom portion BT2 ofstepped portion ST. Next, in second bottom portion BT2 of steppedportion ST, contact electrode 94 a is formed in contact with connectionregion 2 a. Contact electrode 94 a and source electrode 94 may be formedsimultaneously or may be formed separately. Next, source interconnectionlayer 95 is formed in contact with source electrode 94, contactelectrode 94 a, and interlayer insulating film 93. Moreover, drainelectrode 98 is formed on first main surface 10 b constituted of driftregion 81, with silicon carbide single crystal substrate 80 beinginterposed therebetween.

According to MOSFET 1 according to the third embodiment, silicon carbidelayer 10 includes termination region OR and element region IR surroundedby termination region OR. Stepped portion ST is provided in terminationregion OR. Accordingly, p type region 2 can be electrically connected tosource region 83 while securing a wide element region IR.

Fourth Embodiment

Next, the following describes a configuration of a MOSFET 1 according toa fourth embodiment. MOSFET 1 according to the fourth embodiment isdifferent from the configuration of MOSFET 1 according to the thirdembodiment in that connection region 2 a is formed to surround p typeregion 2 when viewed in a plan view. Apart from this, MOSFET 1 accordingto the fourth embodiment has substantially the same configuration asthat of MOSFET 1 of the third embodiment. The following mainly describesthe difference from the configuration of MOSFET 1 according to the thirdembodiment.

With reference to FIG. 16, the following describes the structure ofMOSFET 1 serving as a silicon carbide semiconductor device of the fourthembodiment. In MOSFET 1 according to the fourth embodiment, siliconcarbide layer 10 includes termination region OR and element region IRsurrounded by termination region OR. Connection region 2 a is providedin termination region OR, and may be connected to p type region 2 at aboundary portion between termination region OR and element region IR.When viewed in a plan view, connection region 2 a is a guard ring regionprovided to surround p type region 2. In second bottom portion BT2 ofstepped portion ST, metal region 96 is in contact with connection region2 a serving as the guard ring region. Connection region 2 a serving asthe guard ring region is in contact with p type region 2. In otherwords, metal region 96 is connected to p type region 2 via connectionregion 2 a serving as the guard ring region.

According to MOSFET 1 according to the fourth embodiment, terminationregion OR has guard ring regions 3 having p type. Metal region 96 is incontact with guard ring region 3 in second bottom portion BT2, and guardring region 3 is in contact with p type region 2. Accordingly, thebreakdown voltage of MOSFET 1 can be improved.

Fifth Embodiment

Next, the following describes a configuration of a MOSFET 1 according toa fifth embodiment. MOSFET 1 according to the fifth embodiment isdifferent from the configuration of MOSFET 1 according to the fourthembodiment in that drift region 81 is between field stop region 4 andgate insulating film 91. Apart from this, MOSFET 1 according to thefifth embodiment has substantially the same configuration as that ofMOSFET 1 of the fourth embodiment. The following mainly describes thedifference from the configuration of MOSFET 1 according to the fourthembodiment.

With reference to FIG. 17, the following describes a structure of MOSFET1 serving as a silicon carbide semiconductor device of the fifthembodiment. Field stop region 4 of MOSFET 1 according to the fifthembodiment is provided to be spaced from second main surface 10 a ofsilicon carbide layer 10. Moreover, field stop region 4 may be spacedfrom second bottom portion BT2 of stepped portion ST. In other words,drift region 81 is between field stop region 4 and gate insulating film91. Second main surface 10 a of silicon carbide layer 10 in contact withside end portion 10 d of silicon carbide layer 10 is at a locationseparated from first main surface 10 b of silicon carbide layer 10relative to second bottom portion BT2 of stepped portion ST.

According to MOSFET 1 according to the fifth embodiment, terminationregion OR includes field stop region 4 having n type and surroundingguard ring region 3 when viewed in a plan view. Field stop region 4 isspaced from second main surface 10 a. Accordingly, the breakdown voltageof MOSFET 1 can be improved more.

Sixth Embodiment

Next, the following describes a configuration of a MOSFET 1 according toa sixth embodiment. MOSFET 1 according to the sixth embodiment isdifferent from the configuration of MOSFET 1 according to the fifthembodiment in the following points: drift region 81 is between guardring regions 3 and gate insulating film 91; and metal region 96 isdirectly in contact with p type region 2. Apart from this, MOSFET 1according to the sixth embodiment has substantially the sameconfiguration as that of MOSFET 1 of the fifth embodiment. The followingmainly describes the difference from the configuration of MOSFET 1according to the fifth embodiment.

With reference to FIG. 18, the following describes a structure of MOSFET1 serving as a silicon carbide semiconductor device of the sixthembodiment. Guard ring regions 3 and field stop region 4 of MOSFET 1according to the sixth embodiment are provided to be spaced from secondmain surface 10 a of silicon carbide layer 10. Moreover, guard ringregions 3 may be spaced from second bottom portion BT2 of steppedportion ST. Drift region 81 is between gate insulating film 91 and eachof guard ring regions 3 and field stop region 4. Guard ring regions 3and field stop region 4 are embedded in drift region 81. The connectionregion is p type region 2 substantially in one piece with p type region2, for example. Metal region 96 is directly in contact with p typeregion 2 at second bottom portion BT2 of stepped portion ST.

Furthermore, according to MOSFET 1 according to the sixth embodiment,metal region 96 is directly in contact with p type region 2 in secondbottom portion BT2. Accordingly, the switching characteristic of MOSFET1 can be improved more.

Seventh Embodiment

Next, the following describes a configuration of a MOSFET 1 according toa seventh embodiment. MOSFET 1 according to the seventh embodiment isdifferent from the configuration of MOSFET 1 according to the thirdembodiment in that MOSFET 1 according to the seventh embodiment has aJTE (Junction Termination Extension) region, and metal region 96 is notin contact with second bottom portion BT2 of stepped portion ST. Apartfrom this, MOSFET 1 according to the seventh embodiment hassubstantially the same configuration as that of MOSFET 1 of the thirdembodiment. The following mainly describes the difference from theconfiguration of MOSFET 1 according to the third embodiment.

With reference to FIG. 19, the following describes a structure of MOSFET1 serving as a silicon carbide semiconductor device of the seventhembodiment. MOSFET 1 according to the seventh embodiment has a JTEregion 5. JTE region 5 is a region having p type (second conductivitytype). The dose amount of aluminum ions or the like in JTE region 5 isabout 1.3 to 1.5×10¹³ cm⁻², for example. JTE region 5 is in contact withgate insulating film 91 in second side wall portion SW2 and secondbottom portion BT2 of stepped portion ST. JTE region 5 is in contactwith p type region 2 and body region 82. Source electrode 94 iselectrically connected to p type region 2 via contact region 84, bodyregion 82, and JTE region 5. Contact region 84 is in contact with sourceregion 83. Source region 83 is in ohmic contact with source electrode94. JTE region 5 may be provided to surround p type region 2 when viewedin a plan view.

Next, the following describes an example of a method for manufacturingMOSFET 1 serving as the silicon carbide semiconductor device accordingto the seventh embodiment.

First, a first epitaxial layer forming step (FIG. 20: S10) is performed.The first epitaxial layer forming step is performed in the same manneras described in the first embodiment. Accordingly, lower drift region 81c is formed on silicon carbide single crystal substrate 80. Lower driftregion 81 c includes an impurity such as nitrogen at a concentration of,for example, about 7.0×10¹⁵ cm³. The thickness of lower drift region 81c is about 9 μm, for example.

Next, an embedded p type region forming step (FIG. 20: S20) isperformed. Specifically, an implantation mask (not shown) is used toimplant acceptor ions such as aluminum into lower drift region 81 c,thereby forming p type region 2. The dose amount of aluminum ions isabout 3×10¹³ cm⁻², for example.

Next, a second epitaxial layer forming step (FIG. 20: S30) is performed.After forming p type region 2, upper drift region 81 d having n type isformed on lower drift region 81 c having n type. Accordingly, p typeregion 2 is embedded in drift region 81 constituted of lower driftregion 81 c and upper drift region 81 d. Upper drift region 81 d can beformed by the same method as the method for forming lower drift region81 c. The concentration of the impurity in upper drift region 81 d suchas nitrogen is, for example, about 1.0×10¹⁶ cm³. Upper drift region 81 dhas a thickness of, for example, about 3 μm.

Next, an ion implantation step (FIG. 20: S50) is performed.Specifically, body region 82 and source region 83 are formed on driftregion 81. They can be formed by ion implantation into drift region 81,for example. In the ion implantation for forming body region 82, ions ofan impurity for providing p type such as aluminum (Al) are implanted.Meanwhile, in the ion implantation for forming source region 83, ions ofan impurity for providing n type conductivity such as phosphorus (P) areimplanted, for example. It should be noted that instead of the ionimplantation, epitaxial growth involving addition of impurities may beemployed.

Next, an ion implantation mask layer is formed on second main surface 10a of silicon carbide layer 10 to have an opening in conformity with aregion in which contact region 84 (FIG. 19) is to be formed. Aluminumions or the like are implanted into silicon carbide layer 10 using themask layer, thereby forming contact region 84 having p typeconductivity.

Next, a stepped portion forming step (FIG. 20: S55) is performed. In thestepped portion forming step, the thermal etching described in the firstembodiment is performed. With the thermal etching, stepped portion ST isformed in second main surface 10 a of silicon carbide layer 10. Steppedportion ST includes: second side wall portion SW2 extending to driftregion 81 through source region 83 and body region 82; and second bottomportion BT2 on drift region 81. Preferably, during the formation ofstepped portion ST, the special plane described above is spontaneouslyformed on second side wall portion SW2, in particular, on body region82.

Next, a JTE and GR forming step (FIG. 20: S56) is performed.Specifically, an implantation mask (not shown) is used to implantacceptor ions such as aluminum into second bottom portion BT2 and secondside wall portion SW2 of stepped portion ST, thereby forming JTE region5 in contact with second bottom portion BT2 and second side wall portionSW2 of stepped portion ST, and guard ring regions 3 in contact withsecond bottom portion BT2 of stepped portion ST. The dose amount ofaluminum ions is about 1.3×10¹³ cm⁻², for example. JTE region 5 isformed in contact with p type region 2 and body region 82. Similarly, animplantation mask (not shown) is used to implant donor ions such asphosphorous ions into second bottom portion BT2 of stepped portion ST,thereby forming field stop region 4 in contact with second bottomportion BT2 of stepped portion ST.

Next, an activation annealing step (FIG. 20: S60) is performed. In orderto activate the impurities implanted in silicon carbide layer 10 by theion implantation step, heat treatment is performed onto silicon carbidelayer 10. This heat treatment is preferably performed at a temperatureof not less than 1500° C. and not more than 1900° C., for example, atemperature of approximately 1700° C. The heat treatment is performedfor approximately 30 minutes, for example. The atmosphere of the heattreatment is preferably an inert gas atmosphere, such as Ar atmosphere.

Next, a trench forming step (FIG. 20: S70) is performed. In the trenchforming step, thermal etching described in the first embodiment isperformed. Accordingly, trench TR is formed in second main surface 10 aof silicon carbide layer 10. Trench TR includes: first side wall portionSW1 extending to drift region 81 through source region 83 and bodyregion 82; and first bottom portion BT1 on drift region 81. Each offirst side wall portion SW1 and first bottom portion BT1 is distant awayfrom p type region 2. Preferably, during the formation of trench TR, thespecial plane is spontaneously formed on first side wall portion SW1, inparticular, on body region 82.

Next, a gate oxide film forming step (FIG. 20: S80) is performed. Gateinsulating film 91 is formed to cover first side wall portion SW1 andfirst bottom portion BT1 of trench TR and second side wall portion SW2and second bottom portion BT2 of stepped portion ST. Gate insulatingfilm 91 may be formed, for example, by thermal oxidation. After theformation of gate insulating film 91, NO annealing may be performedusing nitrogen monoxide (NO) gas as an atmospheric gas. Gate insulatingfilm 91 is formed in contact with JTE region 5, guard ring regions 3,field stop region 4, body region 82, and source region 83.

Next, a gate electrode forming step (FIG. 20: S90) is performed. Gateelectrode 92 is formed on and in contact with gate insulating film 91.Specifically, gate electrode 92 is formed on gate insulating film 91 tofill the region in trench TR with gate electrode 92. Gate electrode 92can be formed by, for example, forming a film of conductor or dopedpolysilicon and performing CMP.

Next, an interlayer insulating film forming step (FIG. 20: S100) isperformed. Interlayer insulating film 93 is formed on gate electrode 92and gate insulating film 91 so as to cover the exposed surface of gateelectrode 92. Interlayer insulating film 93 is formed on and in contactwith gate insulating film 93 formed on second side wall portion SW2 andsecond bottom portion BT2 both constituting stepped portion ST.

Next, a source electrode and drain electrode forming step (FIG. 20:S110) is performed. In order to form an opening in interlayer insulatingfilm 93 and gate insulating film 91, interlayer insulating film 93 andgate insulating film 91 are etched. Through the opening, each of sourceregion 83 and contact region 84 is exposed on second main surface 10 a.Next, on second main surface 10 a, source electrode 94 is formed incontact with each of source region 83 and contact region 84. Next,source interconnection layer 95 is formed in contact with sourceelectrode 94, contact electrode 94 a, and interlayer insulating film 93.Moreover, drain electrode 98 is formed on first main surface 10 bconstituted of drift region 81, with silicon carbide single crystalsubstrate 80 being interposed therebetween.

According to MOSFET 1 according to the seventh embodiment, source region83 is in contact with p type region 2 via body region 82 and JTE region5 having p type. Accordingly, metal region 96 does not need to be formedin order to connect source region 83 and p type region 2 to each other,thereby simplifying the manufacturing process of MOSFET 1.

It should be noted that in each of the embodiments described above, aMOSFET has been exemplified and illustrated as the silicon carbidesemiconductor device, but the silicon carbide semiconductor device maybe an IGBT (Insulated Gate Bipolar Transistor) or the like, for example.Moreover, in each of the embodiments described above, it has beenillustrated that n type corresponds to the first conductivity type and ptype corresponds to the second conductivity type; however, p type maycorrespond to the first conductivity type and n type may correspond tothe second conductivity type.

The embodiments disclosed herein are illustrative and non-restrictive inany respect. The scope of the present invention is defined by the termsof the claims, rather than the embodiments described above, and isintended to include any modifications within the scope and meaningequivalent to the terms of the claims.

REFERENCE SIGNS LIST

1: silicon carbide semiconductor device (MOSFET); 2: second conductivitytype region (p type region); 2 a: connection region; 3: guard ringregion; 4: field stop region; 10: silicon carbide layer; 10 a: secondmain surface; 10 b: first main surface; 10 d: side end portion; 80:silicon carbide single crystal substrate; 81: drift region; 81 a: firstcorner portion (apex); 81 b: second corner portion; 81 c: lower driftregion; 81 d: upper drift region; 82: body region; 83: source region;84: contact region; 91: gate insulating film (insulating film); 92: gateelectrode; 93: interlayer insulating film; 94: source electrode; 94 a:contact electrode; 95: source interconnection layer; 96: metal region;97: protective film; 98: drain electrode; BT1: first bottom portion;BT2: second bottom portion; CL: cell; IR: element region; IS:intersection; OR: termination region; ST: stepped portion; SW1: firstside wall portion; SW2: second side wall portion; TR: trench.

1. A silicon carbide semiconductor device comprising: a silicon carbidelayer having a first main surface and a second main surface opposite tosaid first main surface; and a metal region, said silicon carbide layerincluding a drift region that constitutes said first main surface andthat has a first conductivity type, a body region that is provided onsaid drift region and that has a second conductivity type different fromsaid first conductivity type, and a source region that is provided onsaid body region to be separated from said drift region, thatconstitutes said second main surface, and that has the firstconductivity type, said silicon carbide layer being provided with atrench including a first side wall portion and a first bottom surface,said first side wall portion extending from said second main surface tosaid drift region through said source region and said body region, saidfirst bottom surface being in said drift region, said silicon carbidelayer including a second conductivity type region that is embedded insaid drift region and that has said second conductivity type, saidsecond conductivity type region being separated from said body region,said second conductivity type region being electrically connected tosaid source region, said metal region being in contact with said sourceregion, said source region and said second conductivity type regionbeing electrically connected to each other via said metal region, saidsilicon carbide layer being provided with a stepped portion including asecond bottom surface and a second side wall portion, said second bottomsurface being between said first main surface and said second mainsurface, said second side wall portion connecting said second bottomsurface and said second main surface to each other, said metal regionbeing in contact with said source region in said second main surface andis in contact with said second bottom surface, said second conductivitytype region being arranged in a plane, and said metal region beingdirectly in contact with said second conductivity type region.
 2. Thesilicon carbide semiconductor device according to claim 1, wherein saidsilicon carbide layer includes a termination region and an elementregion surrounded by said termination region, and said stepped portionis provided in said termination region.
 3. The silicon carbidesemiconductor device according to claim 2, wherein said terminationregion has a guard ring region having said second conductivity type, andsaid metal region is in contact with said guard ring region at saidsecond bottom surface, and said guard ring region is in contact withsaid second conductivity type region.
 4. The silicon carbidesemiconductor device according to claim 3, wherein said terminationregion includes a field stop region that surrounds said guard ringregion when viewed in a plan view and that has said first conductivitytype, and said field stop region is spaced from said second mainsurface.
 5. The silicon carbide semiconductor device according to claim2, wherein said metal region is directly in contact with said secondconductivity type region at said second bottom surface.
 6. The siliconcarbide semiconductor device according to claim 1, wherein said siliconcarbide layer includes a termination region and an element regionsurrounded by said termination region, and said stepped portion isprovided in said element region.
 7. The silicon carbide semiconductordevice according to claim 6, wherein said metal region is directly incontact with said second conductivity type region at said second bottomsurface.
 8. The silicon carbide semiconductor device according to claim1, wherein said source region is in contact with said secondconductivity type region via said body region and a JTE region havingsaid second conductivity type.
 9. The silicon carbide semiconductordevice according to claim 1, wherein said first bottom surface of saidtrench surrounds said drift region when viewed in a plan view.
 10. Asilicon carbide semiconductor device comprising: a silicon carbide layerhaving a first main surface and a second main surface opposite to saidfirst main surface; and a metal region, said silicon carbide layerincluding a drift region that constitutes said first main surface andthat has a first conductivity type, a body region that is provided onsaid drift region and that has a second conductivity type different fromsaid first conductivity type, and a source region that is provided onsaid body region to be separated from said drift region, thatconstitutes said second main surface, and that has the firstconductivity type, said silicon carbide layer being provided with atrench including a first side wall portion and a first bottom surface,said first side wall portion extending from said second main surface tosaid drift region through said source region and said body region, saidfirst bottom surface being in said drift region, said silicon carbidelayer including a second conductivity type region that is embedded insaid drift region and that has said second conductivity type, saidsecond conductivity type region being separated from said body region,said second conductivity type region being electrically connected tosaid source region, said second conductivity type region being arrangedin a plane, said metal region being directly in contact with said secondconductivity type region, said silicon carbide layer is provided with astepped portion including a second bottom surface and a second side wallportion, said second bottom surface being between said first mainsurface and said second main surface, said second side wall portionconnecting said second bottom surface and said second main surface toeach other, and said metal region is in contact with said source regionin said second main surface and is in contact with said second bottomsurface.
 11. The silicon carbide semiconductor device according to claim10, wherein said second conductivity type region has a mesh structurewhen viewed in a plan view.
 12. The silicon carbide semiconductor deviceaccording to claim 11, wherein said source region and said secondconductivity type region are electrically connected to each other viasaid metal region.
 13. The silicon carbide semiconductor deviceaccording to claim 11, wherein said source region is in contact withsaid second conductivity type region via said body region and a JTEregion having said second conductivity type.
 14. The silicon carbidesemiconductor device according to claim 13, wherein said first bottomsurface of said trench extends to surround a polygonal cell when viewedin a plan view, and when viewed in a plan view, said second conductivitytype region is provided at a location at which an apex of said celloverlaps with said second conductivity type region.
 15. The siliconcarbide semiconductor device according to claim 11, wherein said firstbottom surface of said trench surrounds said drift region when viewed ina plan view.
 16. The silicon carbide semiconductor device according toclaim 10, wherein said first bottom surface of said trench surroundssaid drift region when viewed in a plan view.